LTC1750IFW#PBF【PDF 9/20 页】IC ADC 14BIT 80MSPS SMPL 48TSSOP

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LTC1750

1750f

APPLICATIO S I FOR ATIO

Output Loading

As with all high speed/high resolution converters the

digital output loading can affect the performance. The

digital outputs of the LTC1750 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

output may be used but is not required since the ADC has

a series resistor of 43

on chip.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Format

The LTC1750 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MSBINV pin; high selects offset binary.

Overflow Bit

An overflow output bit indicates when the converter is

overranged or underranged. When OF outputs a logic high

the converter is either overranged or underranged.

Output Clock

The ADC has a delayed version of the ENC input available

as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system.

This is necessary when using a sinusoidal encode signal.

Data will be updated just after CLKOUT falls and can be

latched on the rising edge of CLKOUT.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

example if the converter is driving a DSP powered by a 3V

supply then OVDD should be tied to that same 3V supply.

OVDD can be powered with any voltage up to 5V. The logic

outputs will swing between OGND and OVDD.

GROUNDING AND BYPASSING

The LTC1750 requires a printed circuit board with a clean

unbroken ground plane. A multilayer board with an inter-

nal ground plane is recommended. The pinout of the

LTC1750 has been optimized for a flowthrough layout so

that the interaction between inputs and digital outputs is

minimized. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track or

underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as

shown in the block diagram on the front page of this data

sheet. Bypass capacitors must be located as close to the

pins as possible. Of particular importance are the capaci-

tors between REFHA and REFLB and between REFHB and

LTC1750

1750 F09

OVDD

VDD

0.1

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V TO

VDD

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 9. Equivalent Circuit for a Digital Output Buffer

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